The present invention relates to a semiconductor memory device, and more particularly to a method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices.
Generally, a mask read only memory (hereinafter referred to as a mask ROM) is used for storing a control logic such as a microprogram in an information processing system or the contents of a game in a game chip, or it is used in an office automation equipment and an electronic musical instrument, etc.
Recently, as the more increased storage capacity and the high resolution of a character font and high tone quality in the office automation equipment, electric musical instrument or television game, etc., is carried out, a demand for a cheap and large capacity large-scale integration mask ROM has increased. In order to meet such a demand, a NAND logic mask ROM for increasing integrated degree is disclosed in U.S. Pat. No. 4,142,176. The NAND logic mask ROM has a structure that a plurality of depletion mode transistors and a plurality of enhancement mode transistors are serially connected through a diffusion layer. The NAND logic mask ROM requires only one contact per string. In the NAND logic mask ROM, the string is defined as a group of cells serially connected between each column line and a ground voltage terminal. The NAND logic mask ROM disclosed in the above patent is described with reference to FIGS. 1 to 3.
FIG. 1 shows a partial equivalent circuit diagram of the NAND logic mask ROM and serially connected eight memory cells constitute one string. A first transistor 1 connected to a bit line B/L is a string select transistor and its gate is used as a string select line. Second to ninth transistors 2 to 9 connected between the first transistor 1 and a ground voltage terminal are operated as memory cells. A memory cell array of the NAND logic mask ROM is constructed so that a plurality of memory strings are in parallel connected to the bit line and a memory cell positioned on the same row shares word lines 12 to 19. When performing the reading operation by selecting, for example, the fourth transistor 4, a reading voltage of approximately 1 to 2 volts is applied to a selected bit line, and a power voltage Vcc is applied to the word lines 12, 13, 15, 16, 17, 18 and 19 of the memory cell except for a selected string line 11 and the fourth transistor 4. Meanwhile, the word line 14 of the fourth transistor 4 is grounded. In this case, an unselected bit line, the string select line and an unselected word line are a grounded state. As a result, if the fourth transistor 4 is an enhancement mode, the fourth transistor 4 is turned off by a ground voltage applied to its gate. Thus, since the reading voltage applied to the bit line is cut off, a logic "0" is read out. Moreover, if the fourth transistor 4 is a depletion mode, the fourth transistor 4 is turned on by the ground voltage applied to its gate. Thus, since the reading voltage applied to the bit line is transferred to the fourth transistor 4, a logic "1" is read out. That is, a logic "1" or "0" is read out by applying the ground voltage to the gate of a cell using a depletion transistor of a normally ON type and an enhancement transistor of a normally OFF type.
FIG. 2 is a layout schematic view of a conventional NAND logic mask ROM of FIG. 1. It should be noted that the same parts as those shown in FIG. are designated by like reference numerals. First there is an longitudinally elongated active line 22 which is formed within a semiconductor substrate. The word lines 11 to 19 and a ground line 20 are laterally elongated from the upper portion of the active line 22 and longitudinally disposed in parallel. A metal line 24 is overlapped with the active line 22 from the upper portion of the word lines 11 to 19, and a contact region 26 is for contacting the active line 22 and the metal line 24.
FIG. 3 is cross-sectional view of FIG. 2 taken along the line a--a'. Over the surface of a semiconductor substrate 30 of a first conductivity type, where a field oxide layer 32 is formed, a plurality of gates 11 to 16 interposing a gate oxide layer 34 are formed. A metal layer 24 contacting with a predetermined active region 22 is separated with the plurality of gates 11 to 16 by an insulation interlayer 36. In this case, a plurality of transistors including the gates 11 to 16 are serially connected by the active region 22 formed between the gates 11 to 16. Moreover, each transistor is a programmed state to an enhancement mode or a depletion mode and the gates 11 to 16 are used as word lines.
In case of a conventional NAND logic mask ROM, after forming a polycrystalline silicon (polysilicon) layer, a word line of a memory cell is simultaneously formed by performing a photolithography process. Consequently, spacing between word lines is limited by a limitation of the photolithography process. That is, when forming a pattern by the photolithography process, since the pattern spacing of a photoresist is limited by a resolution limitation of a mask pattern, it is difficult to render the separation spacing between the word lines below the limitation value of the photolithography process. Furthermore, after completing a pattern of the word line, the ion implantation process of impurities is carried out in order to program each memory cell to a wanted mode. To this, during the photolithography process for exposing only a predetermined gate to which impurities are implanted, an accurate alignment of a mask is required. If the alignment of the mask is not accurate, since the impurities are implanted into the neighboring memory cell, the operation of the reliable mask ROM can't be obtained.
Next, a layout schematic view of a conventional NOR logic mask ROM is shown in FIG. 4. A word line 42 parallel to a second direction of a longitudinal direction is extended to a first direction of a transverse direction. An active region 44 is extended to the second direction, and a bit line 46 is overlapped with the active region 44 and formed on the upper portion thereof. A contact region 48 is contacted by the active region 44 and the bit line 46. However, since one contact region is formed with respect to two bits, it has a problem that the entire area is increased.
FIG. 5 is a layout schematic view of another conventional NOR logic mask ROM. The NOR logic mask ROM called a flat cell is available from Sharp Co., and described in "Symposium on VLSI Circuit", 1988, PP. 85 and 86. A word line 50 formed with a polysilicon layer is extended to a first direction of a transverse direction and disposed in parallel to a second direction of a longitudinal direction. A bit line 52 formed with an n+ diffusion layer is disposed in parallel to the first direction and extended to the second direction. When one word line passes neighboring two bit lines, a channel region is formed and the channel region operated as a unit cell 54. Meanwhile, since the bit line is formed with the n+ diffusion layer, only one contact region is formed with respect to a few tens of cells considering the resistance of the bit line instead of one contact region per cell. In the above figure, one contact region is formed with respect to 32 bits. Moreover, since a bit line used as a source or drain of one cell is used as a drain or source of a neighboring cell, the source and drain regions of each cell are reduced to a half in comparison with a conventional mask ROM.
FIG. 6 shows an equivalent circuit diagram of the NOR logic mask ROM shown in FIG. 5. A channel is formed between neighboring two bit lines, and gates in a same row share a word line. When performing reading operation by selecting, for example, a transistor 54, a power source voltage Vcc of approximately 5 volts and a voltage of approximately 2 volts is applied to a bit line B/L1 and a word line W/L2, respectively and a bit line B/L2 is grounded. Moreover, unselected bit lines B/L3, . . . maintain a floating state and unselected word lines W/L1, W/L3, . . . are grounded. As a result, if the threshold voltage of the selected cell is under 2 volts, the selected cell is turned on and the current comes to flow, thereby reading out a logic "1" state.
FIG. 7A is a cross-sectional view of FIG. 5 taken along the line b--b' of a word line direction, and FIG. 7B is a cross-sectional view of FIG. 5 taken along the line c--c' of a bit line direction.
In FIG. 7A, an active region 52 of a second conductivity type formed on a predetermined region of a semiconductor substrate 56 having a first conductivity type is used as a bit line. On the top surface of the substrate 56, a gate oxide layer 60, a word line 50 formed with a polysilicon layer and an insulation layer 62 are successively formed, and a metal layer 58 is formed over the upper portion of the active region 52.
In FIG. 7B, a gate oxide layer 60 is formed on the top surface of the semiconductor substrate 56 of the first conductivity type. Moreover, the word line 50 is formed over a predetermined region of the substrate 56 and the insulation layer 62 is formed over the whole surface of the substrate 56. However, in this case, when performing a pattern, the separation spacing between the word lines is limited by the limitation of the ordinary photolithography process. Meanwhile, as an obstacle factor for reducing the separation spacing between the adjacent word lines to a submicron range, a process margin during ion implantation process for programming the cell should be taken into account. That is, if the separation spacing is the submicron range, since a neighboring cell in addition to a programmed cell is exposed caused by a misalignment or overdevelopment, etc., unwanted data may be stored. Thus, in order to ensure the reliability of products, the word line spacing determining a cell spacing couldn't be reduced to a certain degree.
As described above, in a conventional NAND and NOR logic mask ROMs, since the minimum spacing between the word lines is limited by the limitation of the photolithography process, it has a disadvantage that the achievement of the highly integrated memory device is difficult. Meanwhile, even if the spacing between the word lines becomes a submicron range, during the program of a memory cell, it is difficult to ensure the process margin. Moreover, a very high precision in a process is required for programming only a wanted cell.